Current integrated circuits are chiefly fabricated by planar techniques and the degree of circuit integration that can be achieved on an individual semiconductor chip is reaching saturation. In recent years, a plurality of layers of semiconductor chips are being integrated in a vertical direction in the interest of raising integration efficiency, i.e., semiconductor chips are being stacked one above another and then electrically connected.
In the case of circuits that are integrated vertically, each three-dimensional circuit structure is made up from a stacked unit of individual chip layers (typically joined by layers for adhesive bonding) that have been independently processed and fabricated. To improve the electrical characteristics of connectors in the vertical direction and raise connection density, each individual chip layer is usually produced as a thin film to be of a suitable thickness before assembly.
For example, as the connection construction of circuits that are integrated in the vertical direction, configurations for direct connections between each chip layer are known from publications such as JP-A-2002-305282 (hereinbelow referred to as the “first example of the related art”). FIG. 1 shows a sectional view of a semiconductor device disclosed in the first example of the related art.
As shown in FIG. 1, in this first example of the related art, aluminum pads 103 are provided on semiconductor elements 101 having circuit surfaces 102, and via-holes 110 are provided that pass through these parts. The inner wall surfaces of via-holes 110 are covered by conductive film 112, and gold bumps 104 are arranged on aluminum pads 103. Connections are achieved between semiconductor elements by placing gold bumps 104 of a particular semiconductor element in contact with via-holes 110 on the reverse surface of another semiconductor element.
When a multiplicity of micro-electrodes are connected together in this construction, positioning must be carried out with extreme accuracy at the time of producing the stacked configuration to enable connections at each electrode simultaneously. In addition, problems are encountered that reduce yield such as the difficulty of direct connections caused by the occurrence of a large degree of warping in chips due to thinning or the occurrence of connection defects between electrodes at the time of assembly in this construction. Accordingly, such a construction suffers from the serious drawback of increased fabrication costs due to the reduction of yield and the need for high-accuracy positioning devices.
A non-contact signal transmission method is one method of ameliorating this drawback, an example being disclosed in, for example, JP-A-H08-236696 (hereinbelow referred to as the “second example of the related art”). FIG. 2 shows the configuration of the stacked semiconductor device disclosed in the second example of the related art.
As shown in FIG. 2, transmitter S, and transmission coil SPS connected to this transmitter S are provided on chip layer Ln. Receiver E and reception coil SPE connected to this receiver E are provided on chip layer Ln+x. Transmission coil SPS and reception coil SPE are linked by coupling inductance M. Each chip layer is supplied by power supply devices VSS and VDD. When voltage U1 is received as input from the input side of transmitter S in this semiconductor device, voltage U2 is supplied from the output side, this voltage U2 being applied as input to transmission coil SPS. Voltage U3 is thus induced on the output side of reception coil SPE and voltage U4 is supplied from the output side of receiver E.
In this configuration, a coil is provided that is connected to circuits within one chip layer, another coil is provided connected to the circuits within the other chip layer, and the electromagnetic coupling between the two coils relaxes the conditions regarding positioning (adjustment) between chip layers and the degree of flatness of the surfaces of each of the chip layers compared to the first example of the related art shown in FIG. 1.